1. Field of the Invention
The present invention relates generally to digital transmission in which synchronization is provided by a clock to properly identify and recover a digital signal at a receiving terminal. More specifically, the present invention relates to a digital slip control circuit for either advancing or retarding the timing of the output signal phase of a digital counter without degrading timing performance in high speed applications. The counter slip control technique of the present invention is particularly advantageously applicable to digital phase lock loop circuits, to telecommunications frame synchronization circuits, to high speed elastic buffers, to bit stuffing control counters, to high speed demultiplexers and to channel decoding counter circuits.
2. Description of the Prior Art
Digital signal transmission systems are generally synchronized by means of digital clock signals. Since the digital transmission signals generally include both data (payload) and control (overhead) bits, several frequencies as well as phases of the clock signal are required to completely identify the entire content of the digital transmission signals. Adjustment of a digital counter with a slip control means is well known in the prior art to provide timing signals having various required phases to decompose and identify the contents of a digital signal. As aforementioned, counter slip control is the technique by which a counter output is either advanced or retarded in phase in response to a slip control input pulse.
It is known in the prior art that the counter output phase can be retarded by subtracting a clock pulse and can be advanced by adding a clock pulse. In such known techniques, clock pulses are either added or subtracted by means of a logic gate in series with the clock input to the counter. In high speed counter applications, such prior art techniques are inadequate since the addition of a gate in series with the clock line increases the delay in the timing path, resulting in skew in the timing signals derived at the counter output. Additionally, if clock pulses are added, the gate and the counter are required to operate at twice the normal clock rate, at least momentarily. In high speed logic applications in which the counter is already running at or near the maximum toggle rate, the counter could not operate at the doubled frequency, hence it would be impossible to add a clock pulse.
The present invention avoids the aforementioned deficiencies of the prior art by providing a slip control circuit that does not introduce timing skew in the timing signals derived at the counter output. Also in accordance with the present invention, counter slip control, either phase advancement or phase retardation, can be achieved notwithstanding that the counter is operating at or near its maximum toggle rate of its technology.